Mar 1, 2018 - For many, maybe most, big designs, Apache's RedHawk is the signoff tool for analyzing issues around power: electromigration, power supply. New features in Apache 1.2; New features in Apache 1.1; New features in Apache 1.0. Known Bugs; Compatibility Notes with NCSA httpd; Apache License. Apache Reference Manual. Search the master manual pages for key words Compiling and Installing Apache; Starting Apache; Stopping or Restarting Apache; Apache run-time configuration directives. New CDNS Voltus takes on Apache Redhawk ( ESNUG 534 Item 1 ) -------------------------------------------- [11/08/13] Editor's Note: I love user scoops like this! Looks like Cadence is taking a 2nd run at Apache/Ansys in the IR-drop game. - John ---- ---- ---- ---- ---- ---- ---- Subject: SCOOP -- User reviews new CDNS Voltus that takes on Apache Redhawk > Ansys/Apache RedHawk DMP does full-chip power integrity analysis and > sign-off, transients, simultaneous switching noise including package > and PCB -- but it now has new distributed machine processing (DMP) > that lets it 500 M+ gates, with the accuracy as flat analysis. DMP > did ~2X runtime, ~2.5X less memory vs. Flat simulation. Less than > 2% accuracy loss, 60 M gates and 1.6 B design unknowns on 4 machines. > > - from From: [ A Little Bird ] Hi, John, I know how you like scoops. We've been working with Cadence Voltus, their new unannounced cell-based static/dynamic digital power analysis tool that replaces their present Cadence EPS tool and directly competes against Apache/Ansys Redhawk. Fap dpf off software download. We looked at Redhawk a few years ago and decided to not use it because it couldn't handle our larger design sizes (over 200 M instances) but the newer Cadence EPS could. My comparison is of Cadence EPS (hierarchical) vs. Voltus (hierarchical). Our old power analysis flow went as follows: - VCS simulation - PrimeTime STA - Design Compiler converts Verilog to gates. - Talus/ICC P&R - Read design in gate form (.lib, LEF/DEF, Verilog, VCD files) into EPS. EPS stitches everything together just like how First Encounter does. EPS analyzes total power, static and dynamic IR-drop, and does decap optimations. Gives users the oil maps of IR-drop on the layout. When all block layouts were assembled, EPS took over a week to analyze power at the fullchip level. Download Proxima Nova, font family Proxima Nova by with Regular weight and style, download file name is proximanova-regular.otf. Proxima nova light font free download mac. That throughput was not enough to meet our tape-out schedule. We needed a tool which would handle 200+ M instances with quick turnaround to analyze the effects of our last minute ECOs. ---- ---- ---- ---- ---- ---- ---- Our local Cadence support team gave us a beta version of Voltus. It was a direct swap; took EPS out of our flow; put Voltus in its place. The first big change is Cadence R&D got rid of EPS's 8 power grid views and consolidated them down to 3 Voltus views: Cadence EPS Views Voltus Views ----------------- ------------ Port Early Detailed ---------------> IR Reduced EM Collapsed Quick Detailed Quick Reduced Detailed Dynamic Reduced Dynamic Before, for rail analysis, EPS users had to switch by hand between these 8 power grid views. Now, with Voltus it's been condensed to two views: - XD for accelerated definition and early implementation rail analysis - HD for high definition and final verification IR/EM analysis The other noticeable change was a huge improvement in runtime and multi-CPU scalability for fullchip power and rail analysis.
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